Circuit Laboratory for Advanced Sensors and Systems (CLASS)
The Circuit Laboratory for Advanced Sensors and Systems was founded by Dr. Waleed Khalil in 2009 and is housed in the Electroscience Laboratory (ESL) complex. As part of the Ohio State University Department of Electrical and Computer Engineering, the ESL is a major center-of-excellence that has consistently maintained national and international preeminence in EM and Radio Frequency (RF) circuits & systems.
CLASS is sponsored by contracted research and collaboration with commercial and government organizations. The research is also enabled by shared experimental facilities of the ESL. The lab is equipped with state of the art infrastructure including CAD tools, wafer/package test facilities, and access to in house and external foundries.
Since its establishment, the lab has made significant contributions to RF and mm-wave circuits and systems. Research activities of the lab focus on high-speed wireline and wireless systems and mixed-signal circuits.
ECE 5022-Radio Frequency Integrated Circuits
Modulation, wireless standards, transceiver architecture, transistor models, passive component models, LNA, VCO, PLL, Mixers, integrated PA, RFIC layout.
ECE 7022-Advanced RF Integrated Circuits
Advanced topics on RF and mm-wave circuits. Frequency synthesizers, transmitter linearization techniques (e.g. polar circuits), MIMO and phase array circuits, power D/As.
The Circuit Laboratory for Advanced Sensors and Systems (CLASS), founded by Dr. Waleed Khalil is an internationally acclaimed research group focusing on the areas of high performance mixed signal RF circuits and systems. CLASS collaborates with and is sponsored by governmental and commercial organizations such as the Air Force Research Laboratory, NASA, the National Science Foundation, the Naval Research Laboratory, and others.
CLASS members use powerful simulation and design tools provided by leading electronic design automation (EDA) tool vendors to produce state of the art RF circuit designs. Additionally, CLASS operates a laboratory used to validate and test fabricated ASIC designs. System scale projects can be tested in an ultra-low EMI/RFI interference environment in an 8 ft x 8 ft x 8 ft RF shielded enclosure with 100 dB isolation of EMI/RFI at 10GHz. Devices can also be characterized over temperature using a Tenney T2 environmental chamber. The T2 environmental chamber can accommodate devices up to two square feet in size and produce temperatures ranging from -75˚C to 200˚C.
In the CLASS lab, fabricated ASICs and systems are characterized using an array of precision electrical test equipment. Wafer and die level designs can be probed using probe stations for circuits up to 110 GHz. Other notable equipment includes RF Network Analyzers and signal generators for measurements up to 40GHz and an Agilent Infiniium 54854A oscilloscope with 4 GHz bandwidth.
(left) Tenney T2 environmental chamber used for thermal cycling and characterization of devices over temperature. (center) CLASS laboratory setup for characterizing a high speed Delta-Sigma Digital to Analog Converter ASIC. (right) EMI/RFI shielding room used for testing and calibration of sensitive circuits and systems.
Dr. Waleed Khalil received his B.S.E.E. and M.S.E.E degrees from the University of Minnesota in 1992 and 1993, respectively, and his Ph.D. degree from Arizona State University in 2008. He is currently serving as an Associate Professor at the ECE department and the ElectroScience Lab, The Ohio State University. He is a founder of CLASS (Circuit Laboratory for Advanced Sensors and Systems) at OSU where he conducts research in digital intensive RF and mm-wave circuits and systems, high performance clocking circuits, GHz A/D and D/A circuits. Prior to joining OSU, Dr. Khalil spent 16 years at Intel Corporation where he held various technical and leadership positions in wireless and wireline communication groups. While at Intel, he was appointed the lead engineer at the advanced wireless communications group, where he played an instrumental role in the development of the industry's first Analog Front-end IC for third generation radios (3G). He established Intel's first analog device modeling methodology for mixed signal circuit design and also contributed to the development of Intel's first RF process technology. He later co-founded a startup group to develop Intel's first RF front-end IC, as a principle leader of the radio transmitter chain. He authored and co-authored 11 issued and several other pending patents, over 50 journal and conference papers and three book/book chapters. Dr. Khalil is a senior member in IEEE and serves in the steering committee for the RFIC Symposium and the technical program committee for the Compound Semiconductor IC Symposium (CSICS).
Dr. Dale Shane Smith earned his BS (2005), MS (2011), and PhD (2013) in Electrical and Computer Engineering from The Ohio State University.
Before joining ESL, Shane worked for more than 15 years in the Department of Physics at the Ohio State University designing, producing, and maintaining electronic systems deployed in leading scientific experiments in the U.S. and abroad. As a part of this work, Dr. Smith was involved in a wide range of activities including the design and development of nanometer scale radiation hard mixed signal ASICs, FPGA based data acquisition systems, medical imaging electronics, chemical vapor deposition diamond detectors, and high voltage power supply systems. His publications relating to this research include 11 journal papers and 8 conference papers. His current research interests include radiation hard mixed signal circuits, high reliability integrated circuits, low noise circuits, and high speed and high resolution Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs).
Prof. Eslam Yahya Tawfik leads a research team in the area of Digital SoC Design, Hardware Security & Assurance, AI / Machine Learning, and Secure Hardware Accelerators. He is currently serving as a research Assistant Professor at the ECE department, The Ohio State University. Prior to joining OSU, he served as Assistant Professor in the American University in Cairo, an Assistant Professor in Benha University Egypt, and research associate in INPG France. Prof. Tawfik research got funded by different government and industry agencies such as AFRL, SRC, ADI, Intel, Mentor Graphics, and STMicroelectronics. He is an IEEE Senior Member and he has served as an Organizer, Program Chair, a Technical Program Committee member and a regular Reviewer for several international conferences and journals. In addition to his research activities, Prof. Tawfik has proven teaching experience in digital design, computer engineering, and computer science curriculums.
Mo'men Abusareya received his B.Sc. and M.Sc. degrees in electronics and communications engineering from Ain Shams University, Cairo, Egypt in 2010 and 2016, respectively, In 2010 he joined the design team of Silicon Vision LLC, Egypt (Currently part of Synopsys MSIP solution group). He was involved with the development of high speed serial interface circuits, High and low power DC-DC converter solutions and low power wireless transceivers. In 2015 through 2017 Mo’men led a design team on Synopsys MSIP developing Bluetooth LE transceiver IP. His current research interests is radiation hard diamond sensor interfacing.
Jim Alverson Bio coming soon...
Chris Creech graduated from OSU in December of 2016 with a B.S. in Electrical and Computer Engineering. During school he held an internship focused on computational electromagnetics modeling and simulation. He was also a research assistant for the ESL focusing on printed circuit board design. Upon graduation, Chris became an electrical design and analysis engineer for the Space Launch Systems rocket program with The Boeing Company. Responsibilities included understanding the entire avionics architecture, analyzing data to verify system requirements, and helping design the time distribution system for the Exploration Upper Stage. He authored a research paper based on his time distribution work. In November of 2018, Chris accepted a position as an electrical hardware design engineer for a hypersonic missile program with Lockheed Martin. He was the lead hardware design engineer for the hardware-in-the-loop and system-in-the-loop systems to validate flight software and missile-to-aircraft communications. In April of 2020, Chris joined GLC Technologies, Inc. as the lead electrical engineer helping to execute programs related to trusted microelectronics and hardware assurance. He rejoined OSU in August 2020 to pursue a MS degree in Electrical and Computer Engineering.
Trevor Dean Is from Alpharetta, Georgia. He received his B.S. degree (Magna Cum Laude) in Electrical and Computer Engineering from The Ohio State University in December of 2017. During his undergraduate career, Trevor worked as an intern at Battelle twice, as an intern at ArcelorMittal and as an undergraduate research assistant in the CLASS laboratory. Currently, he is enrolled in the direct to PhD program at The Ohio State University.
Daron DiSabato received B.S. degrees in Communications and Electrical Engineering from Ohio University, Athens, OH, in 2014. He is currently employed as an electronics engineer with The Design Knowledge Company in Fairborn, OH, where he participates in hardware security research activities with the Air Force Research Laboratory. He is concurrently a student researcher at the ElectroScience Laboratory (ESL) and is pursuing a PhD in Electrical Engineering from The Ohio State University, Columbus, OH. Through his work with the ESL, he has participated in research efforts supporting programs sponsored by the Office of Naval Research, the Air Force Research Laboratory, and the Naval Research Laboratory. His research interests include analog and mixed-signal circuit design techniques for device authentication, hardware metering, 2nd order effects mitigation, high-speed I/O transceivers, and integrated data converters.
Mehmet Akif Eker Bio coming soon...
Sam Ellicott is currently working towards his Ph.D. in Electrical and Computer Engineering at Ohio State University. He received his B.S. (Summa Cum Laude) in Electrical Engineering from Cedarville University in 2019. Prior to joining OSU he interned at the Air Force Institute of Technology (AFIT), Automation and Navigation Technology (ANT) center. His current research interests are RF circuit design, hardware obfuscation, and hardware security.
Ahmed Elsayed Bio coming soon...
Roman (Gus) Fragasse (S’14) is currently working towards his Ph.D. in Electrical and Computer Engineering at The Ohio State University. He received B.S and M.S. degrees in Electrical and Computer Engineering from The Ohio State University in 2016, and 2018, respectively. His main areas of focus are analog/mixed-signal and high speed digital integrated circuit design. His previous research interests were focused on techniques enabling high-speed, efficient memory arrays (e.g., SRAM). His current research interests include analog/mixed-signal design techniques for CMOS image sensor design and high-performance read-out integrated circuit (ROIC) design for infrared (IR). Roman has authored or co-authored 4 journal publications and 5 conference publications.
John Hribar Bio coming soon...
Jen-Chieh (Jack) Hsue received his B.S. and M.S. degrees in Electrical and Electronic Engineering from National Cheng Kung University (NCKU) and National Taiwan University (NTU), Taiwan in 2011 and 2014, respectively. He is currently working toward the Ph.D. degree at the Ohio State University. His research is focused on authentication of hardware security.
Michael Kines is currently working towards his Ph.D. in Electrical and Computer Engineering at Ohio State University. He received his B.S. (Summa Cum Laude) and M.S. in Electrical Engineering from The University of Michigan in 2013 and 2015, respectively. Prior to joining OSU, he worked as a Responsible Engineering Authority (REA) on Analog/RF front-ends for missile guidance systems at Raytheon Missile Systems. He is also the recipient of the Distinguished University Fellowship.
Lucas Nestor Bio coming soon...
Lauren Pelan Bio coming soon...
Lindsey Spangler Bio coming soon...
Ramy Tantawy is currently working towards his Ph.D. in Electrical and Computer Engineering at The Ohio State University. He received his B.S. and M.E. (with distinction) degrees in electrical Engineering from Northern Arizona University in 2001 and 2003, respectively.
Prior to joining OSU, Mr. Tantawy spent over 10 years in CMOS mixed-signal circuit design mostly in monolithic CMOS and ROIC imaging applications. From 2002 to 2003, he worked at Intel Corporation, Analog Design Center, in Chandler, AZ, evaluating and developing power management techniques for mobile applications. In 2004, Mr. Tantawy joined Micron Technology, Imagining Center (Now known as Aptina Imaging Corporation), in Pasadena, CA, where he worked for 3 years on the design and development of several CMOS image sensor products for the cellular phone market in the Mobile Image Sensor Group. From 2007 to 2014, Mr. Tantawy worked at Forza Silicon Corporation, in Pasadena, CA, where he participated in various technical, business development and leadership roles to design and develop high-performance CMOS image sensors and ROICs for cinematography, medical, automotive, and defense camera system applications. He authored and co-authored 5 patents, and 4 conference papers.
This section will be updated when we have Visiting Scholars
Parker Carson Bio coming soon...
Gary Sung is an undergraduate student at The Ohio State University. He is pursuing a B.S. in Electrical and Computer Engineering and a business minor through the Integrated Business and Engineering Program (IBE). These interests stem from his high school experience in the FIRST Robotics Competition. As an intern at Wright-Patterson Air Force Base, Gary developed wearable technology using perf board. Then, he was introduced to PCB design while working with small businesses at the Center for Design and Manufacturing Excellence (CDME). Now at ElectroScience Laboratory (ESL), he learned to use Cadence to create a mixed-signal 4-layer PCB for imaging application. Gary hopes to develop skills for the upcoming quantum computing workforce.
Jian Teng (JT) Yan Bio coming soon...
Moataz Abdelfattah (Qualcomm) was born in 1986. He received the B.Sc, and the M.Sc. in electrical engineering from Cairo University, Egypt in 2008, and the American
in Cairo, Egypt, in 2012, respectively. From 2010 to 2012, he was with Intel Corporation, Oregon, U.S. He worked on circuit design for Digital Phase Locked Loops. His research focus is on power management for Near and Sub Threshold circuit design
Saeed Alzahrani received his B.S degree in electronics and communication engineering from King Abdulaziz University, Jeddah, Saudi Arabia, and his M.S degree in electrical engineering from the University of Colorado, Colorado Springs. Currently, he is pursuing the Ph.D. degree at The Ohio State University at ElectroScience lab. His current research interests include the design of ultra-low power voltage controlled oscillators, mixers, frequency multipliers and dividers.
Sidharth Balasubramanian (Texas Instruments) received his B.E. degree in Electronics and Communication Engineering from the College of Engineering, Guindy, (CEG) Anna University, India in 2008. He earned his M.S. and Ph.D. degrees in electrical and computer engineering from The Ohio State University (OSU) in 2009 and 2013, respectively.
He was a member of the on-board electronics team of India's first student-built Microsatellite, ANUSAT, from 2005 to 2008, focusing on the design and integration of RF subsystems at the VHF and UHF range and the on-board computer that were eventually deployed in space in 2009. From 2008 to 2010, he was affiliated with OSU's Analog VLSI Lab, working on low-power circuits for medical SoCs. He spent the fall of 2010 at Xtendwave, a Dallas-based startup, to develop a backward-compatible modulation scheme for WWVB systems, which replaced the legacy scheme in 2012, and is currently the modulation format for broadcasting time in the United States of America. He co-invented a low-power mixed-signal receiver that together with the proposed modulation scheme enables over an order of magnitude in improvement in WWVB reception. From 2009 to 2013, he has been with the ElectroScience Laboratory Complex at OSU, developing theory and circuits for high-speed data conversion, beamforming circuits, mm-wave LC VCOs, etc. Since September 2013, he has been with the high-speed products group at Texas Instruments, Dallas and participates in the product development for high-speed RF data converters. He has authored and co-authored several peer-reviewed publications and a book chapter on advances in digital-to-analog converters.
Dr. Balasubramanian was the recipient of The Ohio State University Fellowship in 2008, Bronze Prize at the 2010 TSMC Outstanding Student Research Award, the 2011 Solid-State Circuits Society Travel Grant Award, the National Science Foundation/MIPR Fellowship in 2011, and the Outstanding Journal Article of ElectroScience Lab award in 2012. He was a two-time nominee for OSU's Presidential Fellowship. He was a co-recipient of the Best Paper Award at the 2013 Wireless Innovation Forum and a student paper contest finalist at the IEEE MWSCAS 2013. He is listed in the Who's Who in America 2015. He is a member of Eta Kappa Nu (HKN), the honor society of the IEEE. He currently serves as the vice-chair of the IEEE Circuits and Systems Society - Dallas Chapter and on the steering and technical program committees of the IEEE Dallas Circuits and Systems Conference, and the Texas Wireless and Microwave Symposiums.
Matthew Belz (Ph.D. Student at University of Michigan) is an undergraduate from Columbus Ohio majoring in Electrical and Computer Engineering. He joined CLASS in 2016 and is pursuing his BSECE with Honors Research Distinction. Matt interned in the RF department at Harris Corporation during the summer of 2017 and worked on jamming resistant radio systems. His current research is focused on mm-Wave VCO modeling and design for RF integrated circuits. In the fall of 2019 he will be starting as a PhD student with Dr. Michael Flynn at the University of Michigan
Matthew Casto (AFRL) received his BS and MS degree in Electrical Engineering in 2003 and 2005 respectively from Wright State University in Dayton, OH. He recieved his PhD from Ohio State University in 2017. He is a member of the IEEE and has authored or co-authored more than 10 publications in the areas of non-linear and electro-thermal device modelling, advanced mixed-signal characterization, and solid state power amplifier design. Dr. Casto is a Branch Chief at the Air Force Research Laboratory's Sensors Directorate and is working on trustworthy, reliable mixed-signal integrated circuits.
Kennedy Caisley is working toward a Ph.D. in Electrical and Computer Engineering at Ohio State University. Prior to joining OSU, he received a B.S. in Electrical Engineering from the University of Idaho in 2019 and interned at Schweitzer Engineering Laboratories designing embedded hardware. In addition to electronics, he enjoys rock climbing and synthesizers.
Justin Dennison (APL) was born and raised in Columbus, Ohio. He received his B.Sc in Electrical and Computer Engineering from the Ohio State University in 2014. Justin is currently working on his Master's Thesis under Prof. Khalil and officially joined C.L.A.S.S group as a GRA in Summer 2015. He has previously worked as a Graduate Teaching Assistant (GTA) in the Engineering Education Innovation Center (EEIC) teaching Fundamental of Engineering Courses at OSU. His research interests include RFICs, wireless communications, mixed signal design, and audio processing.
Luke Duncan (The Design Knowledge Company) earned his B.S. (2009), M.S. (2012), and Ph.D. (2016) degrees in Electrical and Computer Engineering from the Ohio State University. His interests include the design of analog, mixed-signal, and RF circuits. During his M.S. studies, Luke was funded by a Texas Instruments fellowship and completed 12 months of internship experience that included integrated circuit design involving high speed FET switches and a USB3.0/PCIe/SATAIII redriver. His M.S. thesis covers the design of fast-transient low-dropout regulators.
Salma El-Abd (Intel) earned her B.Sc. degree with honours in Electronics and Communication Engineering from the Faculty of Engineering, Ain-Shams University, Cairo, Egypt. She is currently working towards her Ph.D. at The Ohio State University. She was the recipient of The Ohio State University Fellowship in 2010/2011. Her research interests include the design of voltage controlled oscillators and dividers running at the mm-wave frequencies, PLLs, RF PWM modulators, RF power amplifiers, switched DC/DC voltage regulators and current references.
Tim Heaton is currently a masters student working on high speed digital design.
Tyler Heaton is a masters student working on trusted hardware IP infrastructure.
Matthew LaRue (Northrup Grumman) was born and raised in Convoy, OH. In 2012 he graduated magna cum laude from Valparaiso University with a bachelor's degree in electrical engineering. While at Valparaiso University, he served as president of the Tau Beta Pi engineering honor society and conducted research on Quantum-dot Cellular Automata. He is now enrolled in the direct PhD program at The Ohio State University. He is the recipient of the Tau Beta Pi Fellowship, NASA Space Technology Research Fellowship, and a University Fellowship.
Brandon Mathieu (AFRL) is from Bloomingdale, Ohio. He received his B.S. in Computer Engineering (Magna Cum Laude, 2014), M.S. in Electrical Engineering (2015) and is currently working towards his Ph.D in Electrical Engineering all at The Ohio State University. He completed internships at Caterpillar, Chrysler and Advanced Integration LLC during his undergraduate studies. His research interests include mixed signal design, reconfigurable circuits/systems and direct digital synthesis. He received a DAGSI/AFRL fellowship in 2014 & 2015.
Jamin McCue (Northrop Grumman) was born in Clarksburg, West Virginia, in 1987. He received his B.S. degree in Electrical Engineering from Cedarville University in 2009 and subsequently joined the Ohio State University where he earned his Ph.D. His research interests include integrated RF transceivers, high speed mixed signal design, and high speed I/O circuits. Jamin received a fellowship from the AFRL in 2010 and continues to work in association with the AFRL Sensors Directorate.
Ahmed Naguib (Military Technical College) received his B.Sc. degree and the M.Sc with honors in electrical engineering from the Military Technical College (MTC), Cairo, Egypt in 2006 and 2013, respectively. Previously, he was involved in designing low power and low noise circuits for biomedical implantable devices. He is currently working towards his Ph.D in Electrical Engineering at The Ohio State University. His interests include the design of analog, high-speed mixed signal, and RF circuits. His research involves the design and calibration of high speed Digital to Analog Converters (DACs).
S M Shahriar Rashid (Skyworks) is a PhD student of the department of Electrical and Computer Engineering of Ohio State University. He completed his Bachelor and Master's Degrees both from the department of Electrical and Electronic Engineering of Bangladesh University of Engineering and Technology (BUET), Dhaka, Bangladesh in 2009 and 2011 respectively. He is awarded University Fellowship for the year 2012-2013. Previously, he was involved in designing the receiver front end of a high speed intra-chip wireless interconnect system with on-chip integrated antenna. He is currently involved in the design of high power PWM transmitters using GaN technology. Mr. Rashid's research interests include RF, Analog and Mixed Signal Integrated Circuits and Systems. He was the recipient of The Ohio State University Fellowship in 2012/2013.
Chris Taylor is currently working towards his Ph.D. in Electrical and Computer Engineering at The Ohio State University. He received his B.S. (Summa Cum Laude) and M.S. in Electrical Engineering from Wright State University in 2012 and 2014, respectively. Prior to joining OSU he spent 2 years as an electronics research engineer at the Air Force Research Labs Sensors Directorate. His current research interests includes, hardware security, hardware obfuscation and asynchronous design.
Qiyang Wu (Apple) received his M.S. and Ph.D. degrees in Electrical and Computer Engineering from the Ohio State University in 2011 and 2013, respectively. Since 2013, he has been working as an RF engineer at Apple Inc. Prior to that, Dr. Wu was working on mm-wave transceiver and component design. His research interests are in the high-speed digital I/O and RF front-end design for wireless communications. Dr. Wu was the recipient of The Ohio State University Fellowship in 2008 and the NSF/MIPR Fellowship in 2011.
Samantha Yoder (AFRL) received the BS, MS, and PhD degree in electrical engineering from The Ohio State University. She received the SRC Fellowship in 2008, DAGSI fellowship in 2010, and the four-year SMART fellowship in 2011. Her research interests include high-speed digital-to-analog converters, time-based analog-to-digital converters, and delta-sigma modulators. She interned with the Air Force Research Laboratory, Dayton Ohio in the summers of 2011 and 2012.
The Center for Enabling Cyber Defense in Analog and Mixed-Signal Domain (CYAN) is a joint effort hosted by The University of Florida and The Ohio State University. An outstanding research program and team, strong government and industry partnership paired with effective education and capacity building are the fundamentals of CYAN.
The CYAN mission is to establish multidisciplinary research in the area of hardware-enabled cybersecurity through innovation and development of new AMS domain security; addressing a major gap that exists in H/W security’s digital research focus.
If you are interested in learning more about CYAN or would like to view our CYAN Students research, please view our CYAN Website.
Microelectronics security and trust has become and essential and significant component of cybersecurity. National Microelectronics Security Training Center (MEST) is a program that is planning and developing comprehensive training programs in microelectronics design and security.
Distinctive aspects of the MEST program include:
- Collaboration between multiple universities.
- Establishing an ecosystem of training modules and options to suit the need for diverse government and industry employees.
- Strong emphasis on hands-on learning. This includes teaching state-of-the-art computer-aided design tools (CAD) and hands-on hardware design, hacking, and countermeasure tools.
- Major courses and certificate programs
- Comprehensive coverage of all security topics – from devices, architectures, to integrated circuits, to platforms, and to large systems.
- Offering major courses and certificate programs, unique in the nation.
- Self-learning kits for hardware and systems security topic available for remote training and busy professionals.
- Training material made available on secure cloud, e.g. TSS.
Please visit the MEST Website for more details.
Circuit Authentication and Reliability Monitoring
The Integrated Circuit market is continually growing in complexity, performance, capacity, and availability. While these very important parameters are key to technology use and insertion, other, sometimes more critical parameters such as reliability and yield, are degrading. As technology nodes advance with Moore's Law, now approaching 22 and 14 nm, processing capabilities struggle to deal with variability and yield relationships for smallest node implementations. Analyzing information from performance traits may be able to provide quick, accurate correlation to models of reliability and lifetime prediction in operating electronics. This research is focused on developing Mixed-Signal and Radio Frequency design techniques to exhibit unique behavior based on inherent random differences in processing/manufacture. These unique behaviors can be used to identify and group circuits of the same pedigree and provide traits for reliability monitoring.
Digital Beamforming Architecture and Circuits
Conventional analog beamforming topologies, mostly narrowband, suffer from large area, high cost, and high power consumption, due to analog phase shifters and true time delay elements. Conversely, the advancement in digital signal processing, digital beamforming techniques offer more flexibility, while still they suffer from the large number of analog to digital converters (ADC), which exacerbates power consumption and overall size. This research introduces a novel transceiver architecture that permits agile beam forming and jamming mitigation, in addition to offering full MIMO capability. An essential aspect of the new architecture is its departure from the traditional approach of employing individual ADCs for each antenna element. Instead, a single ADC is assigned to a group of array elements, allowing significant reduction in back-end hardware.
Digital Calibration Schemes for GHz-Speed DACs
Modern communication systems require high-Speed high-resolution data converters with sufficient linearity to transfer complex modulations schemes. The current steering architecture is employed due to its switched current configuration which benefits from scaling CMOS processes that offer an improvement in transistor switching speed (i.e. f_T) and reduced device capacitance allowing wideband frequency synthesis with minimal slewing errors. However, an increase in random process mismatch and reduced output impedance generates nonlinear amplitude offsets and timing glitches in the conversion process. The amplitude mismatches effect DAC linearity across the entire Nyquist band, while timing mismatch has a frequency dependent degradation limiting DAC linearity above a few 100 MHz operating frequency. Calibration is required to reduce the mismatch and maintain linearity. Amplitude error calibration has been well developed and silicon proven over the year, however, timing error calibration has just starting being explored. This research hence, focuses on robust and hardware-efficient built in time error calibration techniques.
A DAC model has been developed to assist in the design of a new timing
calibration technique which reduces timing mismatches through modulation of the clock signal’s delay to the DAC retiming latches (termed adaptive clock delay (ACD) calibration). For verification a 14-bit DAC designed in 130nm BiCMOS process (Fig. 1) is designed and fabricated. The DAC uses a 7-bit parallelized LVDS input data stream to generate 14-bits of input data and contains calibration measurement with amplitude and ACD calibration routines. Simulation results show the ACD technique reduces the effect of timing mismatches and significantly improve DAC linearity (Fig. 2) across
operating frequency. Measurement results are pending.
Direct-RF Delta-Sigma Transmitters
Broad adoption of wireless communication forces transceivers to operate in spectrally crowded environments with each mobile generation requiring wider instantaneous bandwidths. This crowded and rapidly changing wireless environment necessitates radios which are flexible with respect to carrier frequency and adaptable with respect to modulation scheme and bandwidth. Critical to these systems are high-performance DACs which facilitate RF synthesis directly from digital inputs.
To meet these demands, a time-interleaved DAC with reconfigurable ΔΣ modulation is proposed. By interleaving, the architecture cancels unwanted replica images which corrupt the output spectrum, enabling multi-Nyquist ΔΣ passbands which increases the low-noise bandwidth of the system. The proposed ΔΣ modulator utilizes a reconfigurable feedback filter to select among several passbands periodically distributed in frequency. Switching between these filter functions enables the design to adaptively generate low-noise signals directly at RF.
High-Speed Digital-to-Analog Converters (DACs)
The lynchpin in future mixer-less radio transmitters is a high-bandwidth digital-to-analog converter. This allows for the implementation of the whole transmitter chain on a single reconfigurable device that supports simultaneous multimode/multiband operation. We have proposed a new class of interleaved RF-DACs, and for the first time in the literature introduced the concept of hold-interleaving in DACs , . This work was featured one among the Top 5 articles in the July 2010 issue of the IET Electronics Letters and was also awarded the 2010 TSMC Outstanding Student Research Award in the circuits category .
We also aim to develop a holistic study and understanding of the micro and macro-level challenges in DAC design, both from the perspective of technology and physical realization. Preliminary results have been presented at the Plenary Talk in the 2012 Compound Semiconductor IC Symposium (CSICS), and have also been published in a book chapter.
High-Speed LVDS Transceivers
Emerging high speed mixed signal circuits require effective means of custom data I/O to support ever-increasing sampling rates. The traditional means of high speed chip-to-chip communication employs a low voltage differential signal (LVDS) scheme. LVDS receivers require either a robust rail-to-rail input stage to accommodate large variation in common mode or a large, off-chip capacitor to couple the incoming signal while allowing the desired common mode to be set on-chip. Rail-to-rail input stages have become less common in advanced processes because of the low breakdown voltage associated with these nodes. The alternative architecture, making use of off-chip coupling capacitors, uses a coding scheme to ensure an adequate number of data transitions. While effective, this method has substantial area and data rate overhead. The proposed architecture uses small, on-chip coupling capacitors before the LVDS amplifier stage to set the common mode on-chip. This topology is advantageous because it removes the need for a rail-to-rail input stage, allows for optimum biasing of the receiver amplifier without regard for the input common mode, and removes the need for discrete components. Data feedback, instead of a coding scheme, is used to ensure lower bit transition rates, which do not sufficiently couple through the on-chip capacitors, are accurately received.
Mixer-Less Direct Digital to RF Transmitters
Available transmitters for SDRs have not yet reached the wholly digital solution as they are still based on heterodyne or homodyne mixing architecture following the digital-to-analog conversion. A feasible solution to realizing a digital transmitter with minimal analog/RF hardware is to completely remove the up-conversion stage which is also the predominant source of nonlinearity in a conventional radio. The proposed technique eliminates the need for heterodyne mixing following the digital-to-analog conversion, a technology deemed critical to meet the SDR forum's definition of the "ideal software radio". Additionally, this architecture can serve as a common architecture that can support multiple radio standards and technologies. Our synopsis of transmitter evolution was published in the IEEE Microwave Magazine.
New Improved System for WWVB Broadcast
The WWVB broadcast of the time-code signal has not undergone major changes in its communications protocol and modulation scheme since its introduction in 1963. Its amplitude-modulation (AM) and pulse-width based representations of its digital symbols were designed to allow for a simple low-cost realization of a receiver based on envelope detection, resulting in poor efficiency in the modulated signal, as with AM audio broadcasting. Over a decade ago, the station's power was significantly increased, allowing the broadcast from Colorado to effectively cover most of North America. This has spurred the popularity of radio-controlled clocks and watches, more commonly known as "atomic clocks". However, electromagnetic interference (EMI) experienced in typical residential and office environments can make it difficult to receive the WWVB signal in various locations.
A new protocol and backward-compatible modulation scheme was proposed and accepted for deployment by NIST to effectively addresses these problems. This will enable greatly improved reception of the WWVB broadcast without impacting the existing devices. The backward-compatibility is achieved by maintaining the existing AM characteristics, while adding various new features through phase modulation (PM). The new modulation scheme and protocol are described and are shown to be effective in addressing these challenges, resulting in several orders of magnitude in performance improvements. Preliminary analyses, including simulated and measured results, were presented to illustrate the challenges encountered in existing receivers, at the 43rd Annual Precise Time and Time Interval (PTTI) Meeting.
Power Management for Near-Threshold Chip Multi-Processors (CMPs)
Power consumption is one of the primary obstacles to the continuation of the exponential growth in the microprocessor performance. The only way to ensure continued growth of the computing industry is to develop solutions that increase the energy efficiency of computation. Operating at supply voltages near the threshold voltage of the transistor (Near-Threshold Computing) is an attractive approach to increase energy efficiency. However, operating at Near-Threshold has the penalty of reduced speed and reliability, and higher sensitivity to process variations. These penalties limit the use of Near-Threshold operation, and make it undesirable for high computation Chip Multi Processors. Our research goal is to develop a power delivery, regulation and management system specific for Near-Threshold operation. The effect of process variation in Near-Threshold voltage range is studied, and ways to reduce the variability are being developed. The expected outcome of the ongoing research is a power management solution that enables high computation technologies to run with high energy efficiency.
Pulse-Width Modulated Digital Transmitters
The demand for high data rate in modern communication systems has accelerated the shift towards complex modulation schemes. This in turn has dictated the need for highly-linear PAs that can meet the Error Vector Magnitude (EVM) requirements for modulation schemes with high peak-to-average power ratio (PAPR) such as 16-QAM, 64-QAM, OFDM, etc. A particular enabling technology for high efficiency PAs is switched-mode operation such as Class D/E/F, where the power transistor is driven into deep ohmic region and behaves as a switch that efficiently modulates the incoming RF signal. This project explores a novel architecture that enables both efficient and linear operation by applying a modulator to translate RF signals with varying envelope into pulses for multiple band operation.
Traditional ADCs are built using analog circuitry that quantize the input signal in the voltage domain (Fig. 1(a)). As technology scales, voltage dynamic range decreases and design difficulties for analog circuits arise. Alternatively, time resolution is improving as technology scales. VCO-based quantizers are highly digital circuits which quantize in the time domain rather than in the voltage domain (Fig. 1(b)), and thus are becoming more attractive in deeply scaled technologies. Early work has used a simple digital counter to quantize the VCO signal. However, issues with the counter "missing" VCO transitions near the sampling clock edge have led to the use of a frequency-to-digital converter (FDC) as the quantization circuit (Fig. 2(a)). The FDC has been widely adopted due to its inherent first order noise shaping characteristic, however, it places a restriction that the sampling frequency must be twice that of the maximum VCO frequency. Another digital time quantization using time-to-digital converters (TDCs) have been traditionally used in phase-locked loops to quantize the VCO phase error, but have not been applied to VCO-based ADCs. This work proposed the use of a delay-line based TDC to quantize the VCO signal (Fig. 2(b)), which only requires that the sampling rate be twice that of the input signal to the VCO. Our results indicate that the VCO nonlinearity (kv) remains the primary bottleneck of these types of quantizers, causing large spurs in the output spectrum (Fig. 3). While both quantizers responded similarly to VCO nonlinearity and phase noise, the TDC was less sensitive to sampling clock jitter. These results were published into a short monograph.
Ultra wide Tuning Range and Low Phase Noise mm-Wave LC VCOs
Over the past few years, there has a been a growing
demand for mm-wave circuits with emerging applications such as Gigabit WLAN and Short Range Radars. More recently, mm-wave technology has been touted for future 5G cellular systems, eclipsing a long era where low GHz systems dominated the field of wireless systems. Moving forward, we expect the mass market adaptation of these technologies to force the shift towards low-cost Si-based processes. However, in order to succeed in this space, we need to push the Si performance closer to the well-entrenched incumbent III-V technologies. In the VCO domain, major challenges still remain in meeting the tuning range and phase noise specifications while maintaining high yield.
In light of these challenges, this research is focused on building mm-wave VCO circuits with record benchmarks. Different topologies in both CMOS and SiGe technologies were developed. Advanced techniques such as active tunable negative capacitance are utilized to break fundamental barriers in silicon based technologies. These new architectures were presented in 2012 IEEE Compound Semiconductor IC Symposium (CSICS), 2013 Transactions on Circuits and Systems - II (TCAS-II) and 2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).
The research also takes an in-depth analysis of phase noise at mm-wave frequencies and proposes a new VCO architecture that incorporates inductance redistribution and BiCMOS cross-coupled pairs with current redistribution to achieve record figure-of-merits (FoM/FoMT). Results from this research were highlighted in 2013 IEEE International Solid State Circuits Conference (ISSCC).
Moreover, a new analytical model that facilitates an efficient optimization of the VCO tuning range and phase noise was developed. The model is also exploited to analyse the impact of CMOS technology scaling on the achievable performance bounds. This analytical model was published in 2013 IEEE International Symposium on Circuits and Systems (ISCAS) and 2014 EEE Transactions on Circuits and Systems - I (TCAS-I).
Students Involved: S. Alzahrani, M. Belz, S. Rashid
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