Fundamentals of Digital IC Design - New Course

COURSE DESCRIPTION:

Digital design flow is a lengthy process that involves many steps to take the design from RTL to the system testing phase. The objective of this course is to demystify this field and provide in-depth understanding of the different transformations that occur in each design step, how these transformations can affect the final performance metrics, and how to tune each step to meet the design specs.

Location
BATTELLE HEADQUARTERS
505 King Avenue
Columbus, Ohio 43201

Can’t  come  to  Columbus?  Attend  and interact remotely!

Avoid the cost  and  hassle of traveling,  and  attend and  interact  remotely  via  an  online meeting with streaming  video.  Instruction  will  be  sent  to  your email.

COURSE DETAILS: This course will focus on fundamental elements in the design process, including HDL modeling, event-driven simulation, synthesis, timing analysis, technology files, standard cell views, physical design, signoff checks, and test planning. Throughout the course, attendees will learn the salient differences in these elements when using FPGA and ASIC platforms. Both Xilinx (for FPGA) and Cadence (for ASIC) design flows will be utilized as part of the training vehicle. VIVADO from Xilinx will cover the entire FPGA flow. On the Cadence side, ASIC simulations will be demonstrated using Incisive, while Genus will be used for synthesis, and Innovus for physical implementation. Finally, Mentor Graphics’ Calibre tool will be used for ASIC signoff checks. The course contains a demonstration project, which will be progressively developed by the trainees throughout the course modules to exercise the two digital design flows. The goal of this course is to provide attendees with understandings of FPGA and ASIC digital flows and to support this understanding with hands-on experience of tools used by industry.

Further Information
Please Contact:
Dr. Eslam Tawfik
Office: +1(614) 292-6657
tawfik.10@osu.edu