Secure Microelectronics and Artificial Intelligence Circuits Lab (SMART)

Prof. Eslam Yahya Tawfik leads a research team in the area of Digital SoC Design, Hardware Security & Assurance, AI / Machine Learning, and Secure Hardware Accelerators. He is currently serving as a research Assistant Professor at the ECE department, The Ohio State University. Prior to joining OSU, he served as Assistant Professor in the American University in Cairo, an Assistant Professor in Benha University Egypt, and research associate in INPG France. Prof. Tawfik research got funded by different government and industry agencies such as AFRL, SRC, ADI, Intel, Mentor Graphics, and STMicroelectronics. He is an IEEE Senior Member and he has served as an Organizer, Program Chair, a Technical Program Committee member and a regular Reviewer for several international conferences and journals. In addition to his research activities, Prof. Tawfik has proven teaching experience in digital design, computer engineering, and computer science curriculums.

LinkedIn Profile

Google Scholar 

Sherif Abouzeid Sherif is a PhD student and a member of SMART team since September 2021. He received his BSc in 2009 in Electrical engineering from Helwan University, Egypt. Sherif received his MSc in 2015 from Nile University in micro-electronics systems design. His research topic was mainly about hardware design of error detection and correction decoders for wireless communication systems. Sherif received his EMBA from MSM, Maastricht School of Management in January 2022 where he majored in Corporates’ finance. Sherif worked for WASEILA - a hardware design house in Egypt - from May 2011 till January 2016 as a hardware design engineer. During his work at WASEILA, he has been involved in ASIC and FPGA projects for wireless communication systems mainly OFDM systems including DVB-C, WIFI 802.11n, LTE and application specific non-standard OFDM projects. He was responsible for developing major design blocks and IP cores, specifically RTL development of synchronization blocks, Forward Error Correction blocks such as LDPC.  Sherif worked as a contractor engineer for CarrierComm – a subsidiary of Moseley group, California - from November 2014 till March 2016. He was responsible for the implementation of their new modem chip clocking and reset scheme. His work included selection of required PLLs and interfacing them with microprocessor, implementation of clock dividers, clock multiplexing scheme, PLL interrupt controllers for locking status, clock gating and reset enables for the entire chip. Sherif joined Riotmicro April 2016. Riotmicro is an IC design company specialized in IOT applications. He was a senior team member of the baseband modem digital design team. Sherif participated in the design and implementation of RM1000 and RM2000 series chips. RM1000 and RM2000 are low power baseband modems implementing LTE-CAT M1 and Narrowband IoT LTE standards. Sherif participated in multiple successful tapeouts for the RM modems. Riotmicro was acquired by STMicroelectronics in September 2020. Sherif worked for STMicroelectronics as a senior hardware design engineer where he was a part of the IOT modem design and implementation team. Sherif’s current research interests includes digital SoC design and implementation, RISC-V processors, opensource EDA tools development and hardware accelerators for AI and machine learning algorithms. Sherif now lives in Columbus, Ohio with his wife and three daughters. Outside of work, he enjoys reading, computer gaming and powerlifting. 

Sherif Elewa received his Bachelor of Science (BSc) and Master of Science (MSc) degrees in Electrical and Computer Engineering at Cairo University Faculty of Engineering in 2010 and 2017, respectively. During his master's studies, he conducted research focused on the hardware design of a timing recovery circuit for the DVB-T2 wireless system receiver.  He is currently a PhD student and member of the SMART team.

Sherif joined WASIELA - hardware design house in Egypt - as a hardware digital design engineer starting from April 2012 till July 2015. During his work at WASIELA he was involved in ASIC and FPGA projects for wireless communication systems such as DVB-T2 and Zigbee low power transceiver. He has also participated in implementing and verifying Dual Clock ADC calibration module for the interfaces between analog and digital circuits. During this period, he participated in the RTL development of some sophisticated IP cores such as timing recovery circuits, frame processing, offset and gain calibration. In addition, he was leading the team performing FPGA prototyping and pre-silicon validation for different solutions. Sherif then joined Mentor Graphics as FPGA prototyping engineer from July 2015 till Feb 2022. He was deeply involved in FPGA prototyping on both single and multiple FPGAs systems using ProFPGA Kits with AXI bus interfaces. During this time, he worked extensively on various technologies of Xilinx FPGAs to bring up complex SoC designs on FPGA. He was involved in heavy validation work to debug complicated design issues such as CDC, timing closure on FPGAs, as well as power aware simulations. He then joined Si-Vision - hardware design house in Egypt - on February 2022 as a staff digital design engineer. His work focus is on the design of the PHY layer architecture for MIPI D-PHY protocol for low-power high-speed serial transmission. He was responsible for leading the project, designing new features, as well as validating the front-end ASIC flow.

Sherif’s research interests include eFPGA, hardware security, and SoC designs targeting FPGA and ASIC.

Islam Elsadek received his B.S degree in Nanotechnology and Nanoelectronics engineering from the University of Science and Technology at Zewail City, Egypt in 2019 with Summa Cum Laude honors. He is currently a Ph.D. student and member of the SMART Team at The Ohio State University, ElectroScience Lab. His current research interests are designing secure and side-channel resistant cryptographic accelerators, such as Lightweight cryptography accelerators, and integrate them into SoCs along with open source GPPs.  

Ahmed Zaky Ghonem received a B.Sc. degree in Nanotechnology & Nanoelectronics Engineering (with honors) from the University of Science and Technology at Zewailcity, Egypt, in 2018. He is currently a Masters student and member of the SMART Team and a Graduate Research Associate with the ElectroScience Lab at The Ohio State University.  Zaky has worked as a Research Engineer at the Agency for Science, Technology, and Research (A*STAR), Singapore, and Nanyang Technological University (NTU), Singapore. He led the design, verification, and implementation of three successful Tapeouts of low-power System-on-Chip (SoCs). The work included,  a RISC-V processor, on/off-chip communication, adapative-performance deep learning accelerators, and non-volatile memories (MRAM and ReRAMs). He was also working as a Research Assistant (RA) at the Center for Nano-electronics and Devices (CND) at the American University in Cairo (AUC), Cairo, Egypt, working on model order reduction and developing algorithms and IPs to EDA software tools for System-on-Chip (SoC) design.  He has authored/co-authored 7 papers in international journals and conferences and was a semi-finalist in the “MEMS Design Contest” organized by Cadence, X-Fab, and Coventor (2017).  His research interests include Low-power SoC Design, Neuromorphic Computing, Hardware Acceleration for AI and Deep Learning,   EDA algorithms, CAD tools development, IoT hardware security, energy harvesting, emerging memory technologies, device modeling.  

Shehab Naga is a PhD student and a member of the SMART Team. He received his B.Sc. in Nanotechnology and Nanoelectronics Engineering, VLSI Concentration with Summa Cum Laude honors from Zewail City, Egypt in February 2023. During his undergraduate studies, he participated in two industrial internships at Si-Vision, Egypt, and PyramidTech, Egypt, one research project at Zewail City, Egypt, and one summer training with Siemens EDA, Egypt. His work spanned the whole ASIC and FPGA design flows, both front and back end. In his last semester as an undergraduate, he worked as a part-time junior FPGA engineer at PyramidTech. His research interests include hardware security, hardware acceleration for AI and machine learning algorithms, and hardware/software co-design.

Jeremy Porter is a PhD student and a member of  the SMART  Team since January of 2020. His research focuses on operating systems, bootloaders, and hardware/software vulnerabilities. He works with open source operating systems such as Linux and a formally verified microkernel seL4. He is developing methods to securely boot operating systems leveraging a chain of trust rooted in hardware. He currently works full time as a Security Engineer and team lead for a small research group as a contractor to government organizations. Prior to becoming a full time contractor, Jeremy worked as an instructor at an educational institution where he taught networking and security courses for ten years.  Jeremy hold a Master’s degree in Cybersecurity from Wright State University and a B.S. in Physics from The Ohio State University. He is a Certified Information Systems Security Professional from (ISC)2 and a Certified Ethical Hacker (CEH). He is interested in all things security including software and hardware security, physical security and human security.  Most recently, Jeremy successfully modified page tables to reduce the memory footprint used by 64-bit RISC-V operating systems. He is now focused on building a reduced footprint, security focused RISC-V bootloader.  Jeremy lives in Columbus with his wife and two sons. He enjoys endurance running, cycling, and indoor rowing. He is an amateur photographer using film and digital infrared.