Secure Microelectronics and Artificial Intelligence Circuits Lab (SMART)

Eslam_Tawfik photo

Eslam Tawfik |  Assistant Professor

Electrical and Computer Engineering

ElectroScience Lab

The Secure Microelectronics and Artificial Intelligence (SMART) Lab was founded by Prof. Eslam Tawfik in 2021. 
Architecting and verifying a SoC is a major step that can happen during the design of the integrated circuit. It incorporates significant design and verification approaches. In the SMART group, we are investigating new methodologies of architecting a wide range of SoCs, varying from resource constrained SoC to Radiation Hardened SoC. Ensuring data flows securely through the entire SoC might include third party or open-source IPs. The SMART group has interests in developing brain inspired accelerators, Domain-Specific Embedded FPGAs, and reduced memory OS for resource constrained devices.   

Lab Capabilities


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Prof. Eslam Yahya Tawfik leads a research team in the area of Digital SoC Design, Hardware Security & Assurance, AI / Machine Learning, and Secure Hardware Accelerators. He is currently serving as a research Assistant Professor at the ECE department, The Ohio State University. Prior to joining OSU, he served as Assistant Professor in the American University in Cairo, an Assistant Professor in Benha University Egypt, and research associate in INPG France. Prof. Tawfik research got funded by different government and industry agencies such as AFRL, SRC, ADI, Intel, Mentor Graphics, and STMicroelectronics. He is an IEEE Senior Member and he has served as an Organizer, Program Chair, a Technical Program Committee member and a regular Reviewer for several international conferences and journals. In addition to his research activities, Prof. Tawfik has proven teaching experience in digital design, computer engineering, and computer science curriculums.

LinkedIn Profile

Google Scholar 

double-arrowGraduate Students

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Sherif Abouzeid Sherif is a PhD student and a member of SMART group since September 2021. he received his BSc in 2009 in Electrical engineering from Helwan University, Egypt. Sherif received his MSc in 2015 from Nile University in micro-electronics systems design. His research topic was mainly about hardware design of error detection and correction decoders for wireless communication systems. Sherif received his EMBA from MSM, Maastricht School of Management in January 2022 where he majored in Corporates’ finance. Sherif worked for WASEILA - a hardware design house in Egypt - from May 2011 till January 2016 as a hardware design engineer. During his work at WASEILA, He has been involved in ASIC and FPGA projects for wireless communication systems mainly OFDM systems including DVB-C, WIFI 802.11n, LTE and application specific non-standard OFDM projects. He was responsible for developing major design blocks and IP cores, specifically RTL development of synchronization blocks, Forward Error Correction blocks such as LDPC.  Sherif worked as a contractor engineer for CarrierComm – a subsidiary of Moseley group, California - from November 2014 till March 2016. He was responsible for the implementation of their new modem chip clocking and reset scheme. His work included selection of required PLLs and interfacing them with microprocessor, implementation of clock dividers, clock multiplexing scheme, PLL interrupt controllers for locking status, clock gating and reset enables for the entire chip. Sherif joined Riotmicro April 2016. Riotmicro is an IC design company specialized in IOT applications. He was a senior team member of the baseband modem digital design team. Sherif participated in the design and implementation of RM1000 and RM2000 series chips. RM1000 and RM2000 are low power baseband modems implementing LTE-CAT M1 and Narrowband IoT LTE standards. Sherif participated in multiple successful tapeouts for the RM modems. Riotmicro was acquired by STMicroelectronics in September 2020. Sherif worked for STMicroelectronics as a senior hardware design engineer where he was a part of the IOT modem design and implementation team. Sherif’s current research interests includes digital SoC design and implementation, RISC-V processors, opensource EDA tools development and hardware accelerators for AI and machine learning algorithms. Sherif now lives in Columbus, Ohio with his wife and three daughters. Outside of work, he enjoys reading, computer gaming and powerlifting. 

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Mika Brattain  is from Boston, MA. He received his B.S. degree in Electrical and Computer Engineering from The Ohio State University in May of 2020. Since graduating, he has been employed at Centauri/KBR performing SoC development and research in firmware and hardware security. He has been a student researcher at the ESL since August of 2021 as part of the SMART program. His technical interests include reverse engineering, penetration testing, machine learning, digital signal processing, and SoC verification. Outside of work and school, he enjoys hiking, running, and chess competitions. 

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Sayed Elgendy (Member, IEEE) is currently a PhD student at The Ohio State University (OSU), Ohio, USA. His research interests are eFPGA, Hardware security, and SoC designs targeting FPGA and ASIC. Before joining OSU, he worked as a research assistant at the National Institute of Informatics (NII), Tokyo, Japan, and Egypt-Japan University for Science and Technology, Egypt. He received the B.Sc. (Hons.) degree in electronics and communications engineering from Al-Azhar University, Cairo, Egypt, and the M.Sc. degree in electronics and communications engineering from Egypt-Japan University for Science and Technology, Egypt.   

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Islam Elsadek received his B.S degree in Nanotechnology and Nanoelectronics engineering from the University of Science and Technology at Zewail City, Egypt in 2019 with Summa Cum Laude honors. He is currently a Ph.D. student at The Ohio State University at ElectroScience lab  Current research interests are designing secure and side-channel resistant cryptographic accelerators, such as Lightweight cryptography accelerators, and integrate them into SoCs along with open source GPPs.  

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Ahmed Zaky Ghonem received a B.Sc. degree in Nanotechnology & Nanoelectronics Engineering (with honors) from the University of Science and Technology at Zewailcity, Egypt, in 2018. He is currently an MSc student & Graduate Research Associate at the ECE department, The Ohio State University, USA.  Zaky has worked as a Research Engineer at the Agency for Science, Technology, and Research (A*STAR), Singapore, and Nanyang Technological University (NTU), Singapore. He led the design, verification, and implementation of three successful Tapeouts of low-power System-on-Chip (SoCs). The work included,  a RISC-V processor, on/off-chip communication, adapative-performance deep learning accelerators, and non-volatile memories (MRAM and ReRAMs). He was also working as a Research Assistant (RA) at the Center for Nano-electronics and Devices (CND) at the American University in Cairo (AUC), Cairo, Egypt, working on model order reduction and developing algorithms and IPs to EDA software tools for System-on-Chip (SoC) design.  He has authored/co-authored 7 papers in international journals and conferences and was a semi-finalist in the “MEMS Design Contest” organized by Cadence, X-Fab, and Coventor (2017).  His research interests include Low-power SoC Design, Neuromorphic Computing, Hardware Acceleration for AI and Deep Learning,   EDA algorithms, CAD tools development, IoT hardware security, energy harvesting, emerging memory technologies, device modeling.  

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Jeremy Porter is a PhD student and a member of  the SMART  group since January of 2020. His research focuses on operating systems, bootloaders, and hardware/software vulnerabilities. He works with open source operating systems such as Linux and a formally verified microkernel seL4. He is developing methods to securely boot operating systems leveraging a chain of trust rooted in hardware. He currently works full time as a Security Engineer and team lead for a small research group as a contractor to government organizations. Prior to becoming a full time contractor, Jeremy worked as an instructor at an educational institution where he taught networking and security courses for ten years.  Jeremy hold a Master’s degree in Cybersecurity from Wright State University and a B.S. in Physics from The Ohio State University. He is a Certified Information Systems Security Professional from (ISC)2 and a Certified Ethical Hacker (CEH). He is interested in all things security including software and hardware security, physical security and human security.  Most recently, Jeremy successfully modified page tables to reduce the memory footprint used by 64-bit RISC-V operating systems. He is now focused on building a reduced footprint, security focused RISC-V bootloader.  Jeremy lives in Columbus with his wife and two sons. He enjoys endurance running, cycling, and indoor rowing. He is an amateur photographer using film and digital infrared. 

double-arrowSMART Alumni

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Security and Trust

Brain-Inspired Computing

CAD Methods and Tools


  • I. Elsadek and E. Y. Tawfik, "RISC-V Resource-Constrained Cores: A Survey and Energy Comparison," 2021 19th IEEE International New Circuits and Systems Conference (NEWCAS), 2021, pp. 1-5, doi: 10.1109/NEWCAS50681.2021.9462781.
  • I. Elsadek and E. Y. Tawfik, "Optimized Design for a Lightweight RISC-V Based Secure Enclave Integrating Standardized Lightweight Cryptography", TECHCON 2022
  • I. Elsadek and E. Y. Tawfik, "Energy Efficiency Enhancement of Parallelized Implementation of NIST Lightweight Cryptography Standardization Finalists" 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2022
  • I. Elsadek and E. Y. Tawfik, "Hardware and Energy Efficiency Evaluation of NIST Lightweight Cryptography Standardization Finalists" 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2022
  • I. Elsadek and E. Y. Tawfik, "Evaluation of Energy Efficiency and Hardware Security of NIST Lightweight Cryptography Final Round Candidates", TECHCON 2021


double-arrowStudent Success

Papers accepted at ISCAS 2022

SMART Lab students had papers accepted at the 2022 International Symposium on Circuits and Systems.